LC network simulating 4ns, 80ohm line

*3.3 volt input source with 1ns delay, 1nS edges, 25ns pulse width, 50ns cycle time
Vin vin 0 1.0 PULSE(0 3.3 1ns 1ns 1ns 25ns 50ns)

*source output impedance of oscillator 
rsrc vin dly_in  68  

L1   dly_in    a           80nh
L2   a         b           80nh
L3   b         c           80nh
L4   c         dly_out     80nh
 
C1    a        gnd         12.5pf
C2    b        gnd         12.5pf
C3    c        gnd         12.5pf
C4    dly_out  gnd         12.5pf

*terminating resistor
R2    dly_out gnd 100Meg


.control
tran 100ps 80ns
plot  V(dly_in) V(dly_out) V(vin)  xl 0.1ns 80ns

*measure the time difference between the input to the network reaching
*1.65V to the output reaching 1.65V...i.e, the delay
meas tran tdiff trig v(dly_in)   val=1.65 rise=1 td=100ps
+               targ v(dly_out)  val=1.65 rise=1 td=100ps

*set hcopydevtype=postscript
*set hcopydev=kec3112-clr
*color0 is background color; color1 grid and text; 2-15 are for the vectors
*set color0 = rgb:f/f/f
*set color1 = rgb:0/0/0
*set color2 = rgb:f/0/0
*hardcopy  out.tmp  V(tline_input) V(join) V(tline_output) xl 5ns 20ns
.endc

.end