Week 7 Self Assessment Quiz Questions

 1.[12] Describe the differences between SPI and TWI in relation to:
       a. Clock (SCL vs SCLK)
       b. Electrical 
          -I/O buffers (do they differ?)
          -Noise immunity (any differences?)
       c. Addressing (differences between addressing methods) 
       d. Speed (difference between SPI and TWI transfer rates)
       e. Wires: How many wires does it take to implement a 4 SPI device interface
          versus 4 TWI devices?)  Assume no extra logic is used.

 2.[3] What does a pullup resistor do?

 3.[8] A complete TWI transfer consists of 4 parts.  Those are:

       1.
       2.
       3.
       4.

 4.[2] What constitutes a repeated start?

 5.[2] Why would a master want to use a repeated start?

 6.[4] If the clock (SCL) is going too fast for a slave, what can the slave
       do about it?

 7.[6] In the address packet, who sends:
       - address
       - R/W
       - ack/nack

 8.[4] How does a slave acknowledge the master at the end of a packet transfer?
       Give which clock pulse and SDA level.

 9.[6] The TWINT bit is used extensively with TWI transfers.  In your own words,
       when TWINT asserts, what does that mean?

10.[4] After every TWINT assertion, what does the TWI status register TWSR hold?


11.[8] You are using an oscilloscope to probe your TWI signals and you see that
       the SDA fall times are about 5nS while the rise times are 10 times
       bigger at about 50nS.  
       a.  Why do think this is?  
       b.  Will your TWI bus still work?   

12.[8] See a circuit for a 3.3v to 5v interface circuit.  Describe in your own words
       how a logic low on the 5 volt side achieves a 0v logic low on the 3.3v logic side. 
       (i.e., no diode drop is experienced) 

13.[2] For the Mega128 EEPROM:  (circle one)
       a) read is slower than write
       b) write is slower than read
       c) they are about the same

14.[2] Under what conditions can we write data to the EEPROM when power is removed from 
       the uC?