Lecture:
M,W,F 1:00PM-1:50PM; KEC 1001
Instructor:
Roger Traylor
E-mail: traylor@ece.NOSPAM.edu
Office: KEC3095
Office Hours: Wednesday, 3:00PM-5:00PM
TAs:
Gurjeet Singh
E-mail: singhg@oregonstate.NOSPAM
Office: Kelley atrium
Office hours: Tu 3-5pm
Jain Sanket
E-mail: jainsa@oregonstate.NOSPAM
Office: Kelley atrium
Office hours: Th 3-5pm
Lyu Tao
E-mail: lyut@oregonstate.NOSPAM
Office: Kelley atrium
Office hours: Fr 2-4pm
Schedule and Assignments
| Week | Dates | Topics | Homework |
|---|---|---|---|
| 1 | Apr 3,5,7 | Architecture and Partitioning Inclass Accumulator Design (sturcture) ----- Architecture and Partitioning (cont.) Inclass Accumulator Design (control and timing) Digital Design Methodology ----- Design Review - 32-bit Multiplier Inclass 32-bit Multiplier Design |
Finish 32-bit multiplier timing and control design |
| 2 | Apr 10,12,14 | About HDLs Verilog modules, ports, instantiation ----- Verilog always blocks Verilog Execution Semantics ----- if/else, unique, priority case, unique, priority |
Top level Verilog of 32-bit multiplier .synopsys_dc.setup file design vision script file test.sv file instructions to help synthesize |
| 3 | Apr 17,19,21 |
Assign Statement The if...else Statement The case Statement initial Block |
Vim System Verilog setup Using Vsim part 1 Using Vsim part 2 |
| 4 | Apr 24,26,28 |
Synchronous Logic Synchronous Logic Blocks ----- Moore-type State Machines system verilog workflow ------ Quiz Quiz 1 Solution In class discussion for 32 bit multiplier |
Finish code and simulation of 32-bit multiplier Homework 2 Due Wednesday next week(May,5,2017) comp_lib.sh In Class quiz Friday May 28th,2017 |
| 5 | May 1, 3,5 |
One-Hot State Machines Mealy State Machines ---------- Scripting bash doit ---------- FPGA_vs_stdcell In class Homework 3 discussion |
Homework 3 due wednesday(May 10th 2017) alu.do wave.do |
| 6 | May 8,10,12 |
Quiz Discussion about Homework 3 verilog_data_types verilog_number_literals verilog_operators Quiz 2 Solution ------------------------- testability In class design Homework 4 -------------------------- In class design FIFO |
Homework 4 Homework 4 (due Wednesday May 17) fifo_skel Testbench input output |
| 7 | May 15,17,19 |
Quiz 3 Quiz 3 Solution FIFO discussion ------------------- Inclass Discussion:GCD ----------------------- Class cancelled due to Undergrad-Expo |
Homework 5 Homework 5 (due wednesday May 24) gcd_rtl_skel.sv Testbench input output |
| 8 | May 22,24,26 |
Quiz 4 Inclass design : GCD FF Setup and hold time Quiz 4 Solution --------------------- Inclass design :TAS ----------------------- Inclass design : TAS |
Homework 6 due(Wednesday June 2) hw6.txt output_data tas_header_def tb.sv |
| 9 | May 29,31,June 2 |
No class on 29th May. (Memorial Day) --------------------------- Inclass design: Homework 7 --------------------------- Quiz 5 (Friday,June 2) Inclass design: Homework 7 What we learned What was forgotten |
Homework 7 due Finals week hw7.txt |
| 10 | June 5, 7, 9 |